Bias circuit for high efficiency complimentary metal oxide semiconductor (cmos) power amplifiers
AssigneeAnalog Devices Global Unlimited Company
InventorsMohamed Moussa Ramadan Esmael, Mohamed Ahmed Youssef Abdalla
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Abstract
Aspects of this disclosure relate to an adaptive biasing circuit for a power amplifier. The adaptive biasing circuit can include a shunt resistor arrangement and/or a floating gate linearizer arrangement.
Claims23
A bias circuit for a power amplifier to enhance linearization of bias ramping for the power amplifier, the bias circuit comprising:
- a field-effect transistor (FET);
- a linearizer arrangement configured to float a gate terminal of the FET to generate a bias signal with quadratic ramping;
- and
- a resistor arrangement electrically connected in parallel with the linearizer arrangement, the resistor arrangement configured to add a linear term to the bias signal, wherein the linearizer arrangement and the resistor arrangement are configured to provide the bias signal at an input of the power amplifier,
- wherein the linearizer arrangement is a floating gate linearizer arrangement that comprises the FET, wherein the FET includes a first terminal, a second terminal, and the gate terminal, wherein the gate terminal is electrically connected to a first end of a first resistor, and wherein the first terminal of the FET is electrically connected to a first node.
(canceled)
A bias circuit for a power amplifier to control bias ramping for a power amplifier, wherein the bias circuit comprises a linearizer arrangement electrically connected to an input of the power amplifier in parallel with a MOSFET, the linearizer arrangement configured to enhance linearity of bias ramping for the power amplifier, wherein the linearizer arrangement is a floating gate linearizer that comprises a first FET, wherein the first FET includes a first terminal, a second terminal, and a gate terminal, wherein the gate terminal is electrically connected to a first end of a first resistor, and wherein a first node is electrically connected to an input of the power amplifier, the first terminal of the first FET, and an alternating power source.
(canceled)
A bias circuit for a power amplifier, the bias circuit comprising a resistor arrangement configured to enhance linearity of bias ramping for the power amplifier, wherein the resistor arrangement is a shunt resistor arrangement that comprises a first resistor, wherein a first end of the first resistor is electrically connected to a first node, the first node is electrically connected to the input of the power amplifier, wherein a second end of the first resistor is electrically connected to a first voltage source.
(canceled)
Dependencies are inferred from the claim text.