Metal landing on top electrode of rram

An integrated circuit (IC), comprising:

• a semiconductor substrate including a memory region and a logic region;
• an interconnect structure disposed over the memory region and the logic region, the interconnect structure including a first lower metal line and a first upper metal line disposed over the memory region and isolated from one another by an interlayer dielectric material, and a second lower metal line and a second upper metal line disposed over the logic region and isolated from one another by the interlayer dielectric material;
• a memory cell or metal-insulator-metal (MIM) capacitor disposed over the memory region and spanning a first vertical distance that separates an upper surface of the first lower metal line from a lower surface of the first upper metal line, the memory cell or MIM capacitor including:
• a bottom electrode disposed over the memory region and coupled to an upper portion of the first lower metal line;
• a data storage or dielectric layer disposed over the bottom electrode;
• and
• a top electrode disposed over the data storage or dielectric layer and coupled to a lower portion of the first lower metal line, wherein the data storage or dielectric layer separates the bottom electrode from the top electrode;
• and
• a logic interconnect structure disposed over the logic region and spanning a second vertical distance that separates an upper surface of the second lower metal line from a lower surface of the second upper metal line, the second vertical distance being equal to the first vertical distance, the logic interconnect structure including:
• a via disposed over the logic region and spanning the entire second vertical distance.

An integrated circuit (IC) comprising:

• a logic device disposed over a logic region of a semiconductor substrate and including a logic interconnect structure thereover, wherein the logic interconnect structure includes a via arranged between a lower metal interconnect layer and an upper metal interconnect layer;
• one or more memory cells disposed over a memory region of the semiconductor substrate and arranged between the lower metal interconnect layer and the upper metal interconnect layer, wherein a memory cell comprises:
• a bottom electrode coupled to the lower metal interconnect layer;
• a data storage layer disposed over the bottom electrode;
• and
• a top electrode disposed over the data storage layer;
• and
• wherein a height of the memory cell over the memory region between the lower metal interconnect layer and the upper metal interconnect layer is equal to a height of the via over the logic region between the lower metal interconnect layer and the upper metal interconnect layer.