Manufacturing techniques and corresponding devices for magnetic tunnel junction devices

An integrated circuit including a magnetoresistive random access memory (MRAM) cell arranged in an interconnect structure over a semiconductor substrate, wherein the interconnect structure includes a lower metal line arranged over a via and an inter-metal dielectric (IMD) layer surrounding the lower metal line and the via, comprising:

• a dielectric protection layer over an upper surface of the lower metal line;
• a bottom electrode including a peripheral portion overlying the dielectric protection layer and a central portion extending through an opening in the dielectric protection layer to contact the upper surface of the lower metal line, wherein the central portion of the bottom electrode has a width that is equal to a width of the via;
• a magnetic tunnel junction over the central portion of the bottom electrode;
• and
• a top electrode over the magnetic tunnel junction.

An integrated circuit including a magnetoresistive random access memory (MRAM) cell arranged in an interconnect structure over a semiconductor substrate, wherein the interconnect structure includes a metal line arranged over a via, comprising:

• an etch stop layer over an upper surface of the metal line;
• a bottom electrode including a peripheral portion overlying the etch stop layer and a central portion extending through an opening in the etch stop layer to contact the upper surface of the metal line;
• a magnetic tunnel junction over the central portion of the bottom electrode, the magnetic tunnel junction having a lower surface at a height that is below a height of the upper surface of the peripheral portion of the bottom electrode;
• a top electrode over the magnetic tunnel junction;
• sidewall spacers arranged over an upper surface of the peripheral portion of the bottom electrode, wherein the sidewall spacers have outer sidewalls which are curved with a monotonically increasing height from the upper surface of the peripheral portion of the bottom electrode to a top surface of the top electrode, wherein a top of the bottom electrode is in direct contact with a bottom surface of the sidewall spacers;
• and
• an inter-metal dielectric layer, adjacent to the sidewall spacers, covering the bottom electrode, the sidewall spacers, and the etch stop layer.