US 2020/0027992 A1Published application

Semiconductor device

AssigneeSamsung Electronics Co., Ltd.

InventorsSOONMOON JUNG, DAEWON HA, SUNGMIN KIM, HYOJIN KIM, KEUN HWI CHO

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Abstract

A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

Claims20

Dependent claims

A semiconductor device, comprising:

a substrate having a plurality of first active patterns, a plurality of second active patterns, a plurality of third active patterns, and a plurality of fourth active patterns,
the plurality of first active patterns being located in a PMOSFET section of a logic cell region of the semiconductor device,
the plurality of second active patterns being located in in an NMOSFET section of the logic cell region,
the plurality of third active patterns in a memory cell region of the semiconductor device, and
the plurality of fourth active patterns being located in between respective ones of the third active patterns, and
the substrate defining a plurality of logic region trenches and a plurality of memory cell region trenches,
the logic region trenches being located between adjacent ones of the first active patterns and between adjacent ones of the second active patterns, respectively, and
the memory cell region trenches being located between adjacent ones of the fourth active patterns and between said respective ones of the third active patterns and the fourth active patterns adjacent thereto, respectively;
and
a device isolation layer disposed in the plurality of logic region trenches and in the plurality of memory cell region trenches, wherein
each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other, and
the memory cell region trenches are deeper than the logic region trenches.

9 more elements

A semiconductor device, comprising:

a substrate having a plurality of first active patterns, a plurality of second active patterns, a plurality of third active patterns, and a plurality of fourth active patterns,
the plurality of first active patterns being located in a PMOSFET section of a first region of the semiconductor device,
the plurality of second active patterns being located in an NMOSFET section of the first region,
the plurality of third active patterns being located in a second region of the semiconductor device disposed laterally of the first region, and
the plurality of fourth active patterns being located in between respective ones of the third active patterns, and
the substrate defining a plurality of first region trenches and a plurality of second region trenches,
the first region trenches being located between adjacent ones of the first active patterns and between adjacent ones of the second active patterns, respectively, and
the second region trenches being located between adjacent ones of the fourth active patterns and between said respective ones of the third active patterns and the fourth active patterns adjacent thereto, respectively;
and
a first device isolation layer disposed in the plurality of first region trenches and in the plurality of second region trenches,
wherein each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other, and
maximum heights of the third and fourth active patterns are greater than maximum heights of the first and second active patterns.

9 more elements

A semiconductor device, comprising:

a substrate having a plurality of first active patterns, a plurality of second active patterns, a plurality of third active patterns, and a plurality of fourth active patterns,
the plurality of first active patterns being located in a PMOSFET section of a first region of the semiconductor device,
the plurality of second active patterns being located in an NMOSFET section of the first region,
the plurality of third active patterns being located in a second region of the semiconductor device disposed laterally of the first region, and
the plurality of fourth active patterns being located in between respective ones of the third active patterns, and
the substrate defining a plurality of first region trenches and a plurality of second region trenches,
the first region trenches being located between adjacent ones of the first active patterns and between adjacent ones of the second active patterns, respectively, and
the second region trenches being located between adjacent ones of the fourth active patterns and between said respective ones of the third active patterns and the fourth active patterns adjacent thereto, respectively;
and
a first device isolation layer disposed in the plurality of first region trenches and in the plurality of second region trenches,
wherein each of the third and fourth active patterns includes first, second, third and fourth semiconductor patterns that are vertically spaced apart from each other.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/504,960Filed 8 Jul 2019
Priority: KR 10-2018-008480720 Jul 2018
Published: 23 Jan 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 30/6733
Characterised by the shapes, relative sizes or dispositions of the gate electrodes: multi-gate TFTs
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…
H10D 30/023
Of FETs having insulated gates [IGFET]: having multiple independently-addressable gate electrodes influencing the same channel
H10D 30/026
Of FETs having insulated gates [IGFET]: having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both…