Techniques for forming vertical transport fet

A method of forming a vertical transport field-effect transistor (VTFET) device, the method comprising the steps of:

• patterning fins in a wafer;
• forming bottom source and drains at a base of the fins;
• forming bottom spacers on the bottom source and drains;
• forming gate stacks over the fins, the gate stacks comprising a gate conductor having a combination of work function metals comprising an outer layer and at least one inner layer of the work function metals;
• isotropically etching the outer layer and the at least one inner layer of the work function metals which, due to the combination of the work function metals, recesses the gate stacks with an outwardly downward sloping profile;
• isotropically etching the at least one inner layer of the work function metals while covering the outer layer of the work function metals to eliminate the outwardly downward sloping profile of the gate stacks;
• forming top spacers above the gate stacks;
• and
• forming top source and drains at tops of the fins over the top spacers.