Fin cut last method for forming a vertical finfet device
AssigneeGlobalfoundries Inc.
InventorsChanro PARK, Kangguo Cheng
Life of this patent
Estimating the term…
Abstract
A fin cut last methodology for manufacturing a vertical FinFET includes forming a plurality of semiconductor fins over a substrate, forming shallow trench isolation between active fins and, following the formation of a functional gate of the active fins, using a selective etch to remove a sacrificial fin from within an isolation region. A further etching step can be used to remove a portion of the gate stack proximate to the sacrificial fin to create an isolation trench and a laterally-extending cavity within the isolation region that are back-filled with an isolation dielectric.
Claims21
1-10. (canceled)
A vertical FinFET structure, comprising:
- a pair of fins disposed over a semiconductor substrate;
- a bottom source/drain region disposed over the semiconductor substrate, where a lower portion of each fins is in contact with the bottom source/drain region;
- a bottom spacer disposed over the bottom source/drain region;
- and
- an isolation structure comprising an isolation dielectric layer disposed between the pair of fins, wherein the isolation structure includes a lower portion having a first width that extends vertically through the bottom spacer into the substrate and between the bottom source/drain region of each fin, and a middle portion above the bottom portion, wherein the middle portion extends laterally over the bottom spacer and has a second width greater than the first width.
A vertical field effect transistor (FET) structure, comprising:
- a pair of active semiconductor regions disposed over a semiconductor substrate;
- a bottom source/drain region disposed over the semiconductor substrate, where a lower portion of each active semiconductor region is in contact with the bottom source/drain region;
- a bottom spacer disposed over the bottom source/drain region;
- and
- an isolation structure comprising an isolation dielectric layer disposed between the pair of active semiconductor regions, wherein the isolation structure includes a lower portion having a first width that extends vertically through the bottom spacer into the substrate and between the bottom source/drain region of each active semiconductor region, and a middle portion above the bottom portion, wherein the middle portion extends laterally over the bottom spacer and has a second width greater than the first width.
A vertical field effect transistor (FET) structure, comprising:
- a pair of active semiconductor regions disposed over a semiconductor substrate;
- a bottom source/drain region disposed over the semiconductor substrate, where a lower portion of each active semiconductor region is in contact with the bottom source/drain region;
- a bottom spacer disposed over the bottom source/drain region;
- a gate stack disposed over sidewalls of the active semiconductor regions, the gate stack extending laterally over the bottom spacer on opposing sides of each active semiconductor region,
- a top spacer disposed over the gate stack;
- a first dielectric layer disposed over the top spacer;
- a top source/drain region disposed over an upper portion of each of the active semiconductor regions;
- a nitride liner disposed between the isolation dielectric layer and each of the top spacer and the bottom spacer, and between the pair of active semiconductor regions, wherein the nitride liner includes a lower portion having a first width that extends vertically through the bottom spacer into the substrate and between the bottom source/drain region of each active semiconductor region, and a middle portion above the bottom portion, wherein the middle portion extends laterally over the bottom spacer and has a second width greater than the first width;
- and
- a shallow trench isolation layer disposed within the semiconductor substrate beneath the middle portion of the isolation structure.
Dependencies are inferred from the claim text.