Transistor structures with reduced parasitic capacitance and improved junction sharpness

A method for forming a nanosheet transistor with reduced parasitic capacitance and improved junction sharpness, the method comprising:

• depositing a bilayer comprising an inner spacer layer and a sacrificial layer on a dummy gate, wherein the dummy gate is formed on a nanosheet stack comprising Si layers and SiGe layers;
• laterally etching the SiGe layers relative to the Si layers such that W is greater than t, wherein W is a lateral etch width and t is a gap distance between Si layers;
• forming an inner spacer adjacent the SiGe layers having a width such that the Si layer has exposed end portions;
• epitaxially growing source/drain regions from the exposed end portions of the Si layer;
• depositing an interlevel dielectric layer;
• selectively removing the dummy gate and remaining portions of the SiGe layers and depositing a high-k dielectric-metal gate structure therein;
• forming contacts in the interlevel dielectric layer to the source/drain regions;
• selectively removing the sacrificial layer to form a gap between the inner spacer layers adjacent the gate and the contacts;
• and
• non-conformally depositing a dielectric into the gap to form an airgap spacer therein.

A method for forming a nanosheet transistor with reduced parasitic capacitance and improved junction sharpness, the method comprising:

• depositing a dummy gate onto the nanosheet stack and sidewalls thereof, the nanosheet stack comprising epitaxially deposited silicon layers sandwiched between SiGe layers;
• depositing a bilayer spacer onto sidewalls of the dummy gate comprising a SiBCN layer in direct contact with the sidewalls and a SiCO sacrificial layer on the SiBCN layer;
• recessing the nanosheet stack to form openings for source or drain regions, wherein the openings are self-aligned to the SiCO sacrificial layer;
• laterally etching the SiGe layers to create a gap between Si layers, wherein W>t, wherein W is a lateral etch width of the SiGe removed and t is a vertical distance between Si layers;
• conformally depositing a first dielectric layer in an amount effective to fill the gap between the Si layers;
• etching back the first dielectric layer to form an inner spacer layer of the first dielectric on sidewalls of the SiGe layers and expose end portions of the Si layers;
• epitaxially growing the source/drain regions from the exposed end portions of the Si layers to the substrate;
• removing the dummy gate and the SiGe layer between the Si layers to form openings therein;
• forming a high-k dielectric-metal gate structure in the openings;
• recessing a top portion of the high-k dielectric-metal gate structure and depositing a dielectric gate cap therein;
• forming contacts to the source or drain regions;
• selectively removing the SiCO sacrificial spacer layer to form a gap between the high-k-metal gate structure and the contacts;
• and
• non-conformally depositing a second dielectric in the gap for form an airgap spacer.