Semiconductor Device with Compensation Structure

A switched-mode power supply comprising a power semiconductor device that comprises:

• a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the drift zone comprising a compensation structure,
• wherein the compensation structure includes first zones of a first conductivity type and second zones of a second, opposite conductivity type, the first and second zones alternately arranged along a horizontal direction orthogonal to a vertical direction, the vertical direction defined by a direct connection line between one of the transistor cells and the drain layer,
• wherein the transistor cells are arranged in an active area of the semiconductor body and an edge area between the active area and a lateral surface of the semiconductor body is devoid of transistor cells, and
• wherein the semiconductor device comprises at least two of the following:
• (1) a smoothed vertical dopant profile in the second zones of the compensation structure in which a dopant concentration of the second zones deviates by not more than 20% as between a local maxima and a local minima of the dopant concentration of the second zones;
• (2) a non-depletable extension zone of the second conductivity type that is electrically connected to body zones of the transistor cells and extends across multiple ones of the second zones at an upper surface of the semiconductor body;
• and
• (3) a low charged edge portion in the edge area having a doping concentration that is lower than portions of the edge area outside the low-charged edge portion.

A semiconductor device, comprising:

• a semiconductor body comprising:
• a drain layer extending to a rear surface of the semiconductor body;
• a drift zone disposed over the drain layer and having a lower dopant concentration than the drain layer;
• an active area comprising one or more transistor cells, each of the transistor cells comprising source zones disposed over the drift zone and extending to a main surface of the semiconductor body that is opposite from the rear surface, and a gate configured to control a conductive channel between the source zones and the drain layer;
• wherein the semiconductor device exhibits a first output charge gradient when a voltage between the drain layer and the source zones increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device,
• wherein the semiconductor device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and
• wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.