Semiconductor device for high voltage isolation

A dual junction field effect transistor (JFET) semiconductor device comprising:

• a first JFET and a second JFET, wherein
• each of the first and second JFETs includes a respective gate region and channel region of opposite conductivity types and forming a diode junction. a drain terminal, a source terminal, and a gate terminal
• the first JFET includes
• a substrate layer of a first conductivity type with a relatively low impurity concentration
• a first region of a second conductivity type and having a relatively low impurity concentration, located in the substrate layer as the channel region of the first JFET,
• first and second conductors located on and in electrical communication with the first region and separated from each other by an electrically insulating isolator layer, wherein the first conductor is the drain terminal of the first JFET and the second conductor is the source terminal of the first JFET for establishing an electrical current can flow between the source terminal and the drain terminal and through the first region without encountering an opposite conductivity type junction,
• a second region of the first conductivity typed and having a relatively high impurity concentration, located in the substrate layer and contacting the first region to form the diode junction of the first JFET, and
• a third conductor, separated from the first and second conductors by the isolator layer, arranged on and in electrical communication with the second region, wherein the third conductor is the gate terminal of the first JFET for establishing a depletion region in the first region and thereby controlling the electrical current flow through the first region, between the source terminal and the drain terminal of the first JFET, and
• the second JFET includes
• a substrate layer of a first conductivity type with a relatively low impurity concentration,
• a first region of the second conductivity type and having a relatively low impurity concentration, located in the substrate layer as the channel region of the second JFET,
• first and second conductors located on and in electrical communication with the first region and separated from each other by an electrically insulating isolator layer, wherein the first conductor is the drain terminal of the second JFET and the second conductor is the source terminal of the second JFET for establishing an electrical current can flow between the source terminal and the drain terminal and through the first region without encountering an opposite conductivity type junction,
• a second region of the first conductivity type and having a relatively high impurity concentration, located in the substrate layer and contacting the first region to form the diode junction of the second JFET, and
• a third conductor, separated from the first and second conductors by the isolator layer, arranged on and in electrical communication with the second region, wherein the third conductor is the gate terminal of the second JFET for establishing a depletion region in the first region and thereby controlling the electrical current flow through the first region, between the source terminal and the drain terminal of the second JFET.