Variable resistance memory device including symmetrical memory cell arrangements and method of forming the same

A variable resistance non-volatile memory device comprising:

• a semiconductor substrate;
• a first conductive line extending in a first direction perpendicular to the semiconductor substrate;
• at least three second conductive lines formed vertically stacked on one another, each of the second conductive lines extending in a second direction parallel to the semiconductor substrate on a first side of the first conductive line;
• at least three third conductive lines formed vertically stacked on one another, each of the third conductive lines extending in the second direction parallel to the semiconductor substrate on a second side of the first conductive line opposite the first side of the first conductive line;
• a plurality of insulating layers, wherein each of the plurality of insulating layers separates two vertically adjacent ones of the at least three second conductive lines from one another and separates two vertically adjacent ones of the at least three third conductive lines from one another;
• at least three first non-volatile memory cells formed stacked on one another on the first side of the first conductive line and coupled to the at least three second conductive lines and separated from one another by ones of the plurality of insulating layers;
• and
• at least three second non-volatile memory cells formed stacked on one another on the second side of the first conductive line and coupled to the at least three third conductive lines and separated from one another by the ones of the plurality of insulating layers.

A variable resistance non-volatile memory device comprising:

• a semiconductor substrate;
• a first conductive line extending in a first direction perpendicular to the semiconductor substrate;
• a plurality of second conductive lines vertically stacked on one another, each of the second conductive lines extending in a second direction parallel to the semiconductor substrate on a first side of the first conductive line;
• a plurality of third conductive lines vertically stacked on one another, each of the third conductive lines extending in the second direction parallel to the semiconductor substrate on a second side of the first conductive line opposite the first side of the first conductive line;
• a plurality of insulating layers, wherein each of the plurality of insulating layers separates vertically adjacent ones of the plurality of second conductive lines from one another and separates vertically adjacent ones of the plurality of third conductive lines from one another;
• and
• a plurality of variable resistance elements simultaneously formed between the plurality of insulating layers to couple to respective ones of the plurality second conductive lines and to respective ones of the plurality of third conductive lines.

A method of forming variable resistance non-volatile memory device, the method comprising:

• forming a structure including alternating insulating layers and sacrificial layers on a substrate;
• forming a plurality of filling insulating layers extending vertically through the structure spaced apart on the substrate;
• forming a first trench through the structure to provide first recessed sidewalls of each of the sacrificial layers through which the first trench passes;
• forming a second trench through the structure, spaced apart from the first trench, to provide second recessed sidewalls of each of the sacrificial layers, opposite the first recessed sidewalls;
• forming a first phase change memory cell portion on each of the first recessed sidewalls;
• forming a second phase change memory cell portion on each of the second recessed sidewalls;
• forming first conductive lines on the first phase change memory cell portion and on the second phase change memory cell portion;
• forming an isolation insulation pattern in the first trench and in the second trench;
• forming a third trench through the structure between first trench and the second trench to expose the first phase change memory cell portion and to expose the second phase change memory cell portion;
• forming a third phase change memory cell portion on each first phase change memory cell portion through the third trench to provide first phase change memory cells;
• forming a fourth phase change memory cell portion on each second phase change memory cell portion through the third trench to provide second phase change memory cells;
• and
• forming a second conductive line in the third trench on the first phase change memory cell and on the second phase change memory cell.