Rram memory cell with multiple filaments
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChin-Chieh Yang, Chih-Yang Chang, Wen-Ting Chu, Yu-Wen Liao
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Abstract
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive element disposed within a dielectric structure over the substrate. The conductive element has a top surface extend between outermost sidewalls of the conductive element. A first resistive random access memory (RRAM) element is arranged within the dielectric structure and has a first data storage layer directly contacting the top surface of the conductive element. A second RRAM element is arranged within the dielectric structure and has a second data storage layer directly contacting the top surface of the conductive element.
Claims20
An integrated chip, comprising:
- a conductive element disposed within a dielectric structure over a substrate, wherein the conductive element comprises a top surface extending between outermost sidewalls of the conductive element;
- a first resistive random access memory (RRAM) element arranged within the dielectric structure and having a first data storage layer directly contacting the top surface of the conductive element;
- and
- a second RRAM element arranged within the dielectric structure and having a second data storage layer directly contacting the top surface of the conductive element.
A memory circuit, comprising:
- a first resistive random access memory (RRAM) element arranged within a dielectric structure over a substrate and having a first lower electrode;
- a second RRAM element arranged within the dielectric structure and having a second lower electrode, wherein the dielectric structure comprises an insulating layer laterally surrounding the first lower electrode and the second lower electrode, the first lower electrode and the second lower electrode continuously extending from directly between sidewalls of the insulating layer to above a top surface of the insulating layer;
- and
- wherein the first lower electrode is coupled to the second lower electrode by a lower interconnect layer disposed within the dielectric structure at a location between the first lower electrode and the substrate.
A memory circuit, comprising:
- a control device;
- a first resistive random access memory (RRAM) element coupled between a first terminal of the control device and a first bit-line;
- a second RRAM element coupled between the first terminal of the control device and a second bit-line;
- and
- a sensing element operably coupled to the first bit-line and to the second bit-line and configured to read a single data state from the first bit-line and the second bit-line.
Dependencies are inferred from the claim text.