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US 2020/0027907 A1Published application
Slt integrated circuit capacitor structure and methods
AssigneepSemi Corporation
InventorsAbhijeet Paul, Hiroshi Yamada, Alain Duvallet
Life of this patent
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AssigneepSemi Corporation
InventorsAbhijeet Paul, Hiroshi Yamada, Alain Duvallet
Estimating the term…
FET IC structures that enable formation of integrated capacitors in a “flipped” SOI IC structure made using a back-side access process, such as a “single layer transfer” (SLT) process, and which eliminate or mitigate unwanted parasitic couplings to a handle wafer. In some embodiments, a conductive interconnect layer may be patterned, pre-SLT, to form an isolated first capacitor plate. In other embodiments, pre-SLT, a conductive region of the active layer of an IC may be patterned to form an isolated first capacitor plate, with one or more interconnect layers being fabricated in position to form an electrical contact to the first capacitor plate. In either case, a post-SLT top-side layer of conductive material may be patterned to form a second capacitor plate. Couplings to the resulting capacitor structures include only external connections, only internal connections, or both internal and external connections
An inverted integrated circuit structure attached to a handle wafer and including:
-12. (canceled)
An inverted integrated circuit structure attached to a handle wafer and including:
-26. (canceled)
An integrated circuit structure including:
-50. (canceled)
Dependencies are inferred from the claim text.