Manufacturing method of array substrate and array substrate

A manufacturing method of an array substrate, comprising steps of:

• depositing a first metal layer on an in-plane region and an out-of-plane region of the substrate;
• depositing a gate insulating layer on the substrate and the first metal layer, and forming a first via hole in the in-plane region of the gate insulating layer, wherein the first via hole directly reaches a surface of the first metal layer of the in-plane region;
• depositing a second metal layer in the in-plane region and the out-of-plane region of the gate insulating layer, wherein the second metal layer located in the in-plane region fills the first via hole;
• depositing a passivation layer on the second metal layer and the gate insulating layer, and forming a second via hole in the in-plane region of the passivation layer, which directly reaches a surface of the second metal layer of the in-plane region;
• forming a third via hole in the out-of plane region of the passivation layer, which directly reaches a surface of the second metal layer of the out-of plane region, and forming a fourth via hole in the out-of plane region of the passivation layer, which directly reaches a surface of the first metal layer of the out-of plane region;
• depositing a transparent conductive layer in the in-plane region and in the out-of-plane region of the passivation layer, respectively, and the transparent conductive layer in the in-plane region fills the second via hole, and the transparent conductive layer in the out-of-plane region fills the third via hole and the fourth via hole.