Array substrate
AssigneeShenzhen China Star Optoelectronics Technology Co., Ltd.
InventorCHING FU CHIEN
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Abstract
The array substrate taught by the present invention have dummy ITO lines on the fanout lines configured as multiple segments separated at intervals so that, when two neighboring dummy ITO lines are short-circuited, the place of short circuit is limited to a segment of the neighboring dummy ITO lines. Coupling capacitance is limited to that between the segments and fanout lines. Compared to prior arts where coupling capacitance occurs between neighboring dummy ITO lines and fanout lines, the present invention has much smaller coupling capacitance, thereby reducing the impact of coupling capacitance to signal transmission on the fanout lines, avoiding the occurrence of light lines on the display panel, and enhancing the display effect of the display panel.
Claims17
An array substrate, comprising a display area, a non-display area surrounding the display area, a plurality of signal lines within the display area, control chips within the non-display area, a plurality of fanout lines separated at intervals within the non-display area, a plurality dummy indium tin oxide (ITO) lines separated at intervals within the non-display area, and a first insulation layer, wherein each fanout line has an end connected to a control chip and another end connected to a signal line, the dummy ITO lines are stacked above the fanout lines, the dummy ITO lines and the fanout lines are separated by the first insulation layer, each fanout line corresponds to a dummy ITO line, and each dummy ITO line comprises a plurality of ITO segments separated at intervals along an extension direction of a corresponding fanout line.
Dependencies are inferred from the claim text.