Three-dimensional semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung Hwan SON, Seo Goo KANG, Shin Hwan KANG
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Abstract
A three-dimensional semiconductor memory device includes: gate electrodes and mold insulation layers alternately stacked on a substrate; a channel layer passing through the gate electrodes and the mold insulation layers; and a gate dielectric layer between the gate electrodes and the channel layer. The gate dielectric layer and the channel layer may be in an upper portion of the substrate and may be bent at a first angle and extend under the mold insulation layers in the upper portion of the substrate.
Claims20
A three-dimensional semiconductor memory device comprising:
- gate electrodes and mold insulation layers alternately stacked on a substrate;
- a channel layer passing through the gate electrodes and the mold insulation layers;
- and
- a gate dielectric layer between the gate electrodes and the channel layer,
- wherein the gate dielectric layer and the channel layer are in an upper portion of the substrate, bent at a first angle, and extend under the mold insulation layers in the upper portion of the substrate.
A three-dimensional semiconductor memory device comprising:
- gate electrodes and mold insulation layers alternately stacked on a substrate;
- and
- a channel structure passing through the gate electrodes and the mold insulation layers, and in a recess in an upper portion of the substrate,
- wherein a width of the channel structure gradually decreases toward the substrate, and increase again in the upper portion of the substrate.
A three-dimensional semiconductor memory device comprising:
- a substrate having a recess;
- gate electrodes and mold insulation layers alternately stacked on the substrate;
- a channel hole passing through the gate electrodes and the mold insulation layers;
- and
- a channel structure in the channel hole and in the recess of the substrate,
- wherein at least a portion of the recess has a width wider than a width of a lower portion of the channel hole.
Dependencies are inferred from the claim text.