Three-dimensional semiconductor device

A three-dimensional semiconductor device comprising:

• a peripheral circuit structure disposed on a lower substrate, and including an internal peripheral pad portion;
• an upper substrate disposed on the peripheral circuit structure;
• a stack structure disposed on the upper substrate, and including gate horizontal patterns;
• separation structures disposed on the upper substrate, and passing through the stack structure;
• a vertical channel structure disposed on the upper substrate, and passing through the stack structure;
• a vertical support structure disposed on the upper substrate, and passing through the stack structure;
• and
• a peripheral contact structure passing through and extending downwardly from the stack structure and the upper substrate in sequence, and contacting the internal peripheral pad portion,
• wherein the vertical channel structure comprises material layers different from a material layer constituting the vertical support structure, and
• wherein an upper surface of the peripheral contact structure and an upper surface of the vertical support structure are located on a level higher than an upper surface of the vertical channel structure.

A three-dimensional semiconductor device comprising:

• a peripheral circuit structure disposed on a lower substrate, and including an internal peripheral pad portion;
• an upper substrate disposed on the peripheral circuit structure;
• a stack structure disposed on the upper substrate, and including gate horizontal patterns, wherein the gate horizontal patterns are stacked in a vertical direction, perpendicular to an upper surface of the upper substrate while being spaced apart from each other in a first region on the upper substrate, extend lengthwise from the first region in a horizontal direction parallel to the upper surface of the upper substrate, and comprise pad regions arranged in a stepped manner in a second region on the upper substrate;
• separation structures disposed on the upper substrate, traversing the first region and the second region, and passing through the stack structure;
• a vertical channel structure disposed in the first region on the upper substrate, and passing through the stack structure, between the separation structures;
• a vertical support structure disposed in the second region on the upper substrate, and passing through the stack structure, between the separation structures;
• and
• a peripheral contact structure contacting the internal peripheral pad portion, extending upwardly, and sequentially passing through the upper substrate and the stack structure,
• wherein upper surfaces of the separation structures, the peripheral contact structure, and the vertical support structure are located on a level higher than an upper surface of the vertical channel structure.