Methods for forming three-dimensional memory devices

A method for forming a three-dimensional (3D) memory device, comprising:

• forming a peripheral device on a first substrate;
• forming, on the first substrate, a first interconnect layer above the peripheral device;
• forming a plurality of memory strings each extending vertically on a second substrate;
• forming, on the second substrate, a second interconnect layer above the memory strings;
• forming, on the second substrate, a dielectric stack comprising a plurality of dielectric/sacrificial layer pairs through which the memory strings extend vertically,
• bonding the first substrate and the second substrate, so that the first interconnect layer is below and in contact with the second interconnect layer;
• thinning the second substrate after the bonding;
• and
• forming a memory stack below the thinned second substrate and comprising a plurality of conductor/dielectric layer pairs, wherein edges of the conductor/dielectric layer pairs in a staircase structure of the memory stack along a vertical direction away from the first substrate are staggered laterally toward the memory strings,
• wherein forming the memory stack comprises forming the staircase structure at an edge of the dielectric stack and replacing sacrificial layers in the dielectric/sacrificial layer pairs by a plurality of conductor layers, and
• forming the staircase structure comprises performing a plurality of trim-etch cycles for the dielectric/sacrificial layer pairs toward the first substrate.

A method for forming a three-dimensional (3D) memory device, comprising:

• forming a peripheral device on a first substrate;
• forming, on the first substrate, a first interconnect layer above the peripheral device;
• forming, on a second substrate, a dielectric stack comprising a plurality of dielectric/sacrificial layer pairs and a plurality of memory strings each extending vertically through the dielectric stack;
• forming, on the second substrate, a second interconnect layer above the memory strings;
• bonding the first substrate and the second substrate, so that the first interconnect layer is below and in contact with the second interconnect layer;
• thinning the second substrate after the bonding;
• and
• forming a memory stack below the thinned second substrate and comprising a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, sacrificial layers in the dielectric/sacrificial layer pairs,
• wherein forming the memory stack comprises etching an opening through the thinned second substrate and the plurality of dielectric/sacrificial layer pairs, etching the sacrificial layers in the plurality of dielectric/sacrificial layer pairs through the opening, and depositing the conductor layers in the plurality of conductor/dielectric layer pairs through the opening.

A method for forming a three-dimensional (3D) memory device, comprising:

• forming a peripheral device on a first substrate;
• forming, on the first substrate, a first interconnect layer above the peripheral device;
• forming a plurality of memory strings each extending vertically on a second substrate;
• forming, on the second substrate, a second interconnect layer above the memory strings;
• forming, on the second substrate, a dielectric stack comprising a plurality of dielectric/sacrificial layer pairs through which the memory strings extend vertically,
• bonding the first substrate and the second substrate, so that the first interconnect layer is below and in contact with the second interconnect layer;
• thinning the second substrate after the bonding;
• and
• forming a memory stack below the thinned second substrate and comprising a plurality of conductor/dielectric layer pairs, wherein edges of the conductor/dielectric layer pairs in a staircase structure of the memory stack along a vertical direction away from the first substrate are staggered laterally toward the memory strings,
• wherein forming the memory stack comprises forming the staircase structure at an edge of the dielectric stack and replacing sacrificial layers in the dielectric/sacrificial layer pairs by a plurality of conductor layers, and
• replacing the sacrificial layers comprises etching an opening through the thinned second substrate and the plurality of dielectric/sacrificial layer pairs, etching the sacrificial layers in the plurality of dielectric/sacrificial layer pairs through the opening, and depositing the conductor layers in the plurality of conductor/dielectric layer pairs through the opening.