Semiconductor device and manufacturing method thereof

A semiconductor device including:

• a non-volatile memory cell formed in a memory cell area of a substrate;
• a first circuit formed in a first circuit area of the substrate;
• a second circuit formed in a second circuit area of the substrate;
• and
• a third circuit formed in a third circuit area of the substrate, wherein:
• a device forming surface is defined as an interface between a gate dielectric layer and a channel,
• a first device forming surface of the substrate in the first circuit area is located at a lower level than a second device forming surface of the substrate in the second circuit area as viewed in cross section, and
• a memory cell forming surface of the substrate in the memory cell area is located at a same level as or at a lower level than the first device forming surface of the substrate in the first circuit area as viewed in cross section.

A semiconductor device including:

• a non-volatile memory cell formed in a memory cell area of a substrate;
• a first circuit including a first FET formed in a first circuit area of the substrate;
• a second circuit including a second FET formed in a second circuit area of the substrate;
• a third circuit including a third FET formed in a third circuit area of the substrate;
• a fourth circuit including a fourth FET formed in a fourth circuit area of the substrate;
• a fifth circuit including a fifth FET formed in a fifth circuit area of the substrate;
• and
• a sixth circuit including a sixth FET formed in a sixth circuit area of the substrate, wherein:
• a device forming surface is defined as an interface between a gate dielectric layer and a channel,
• a first device forming surface of the substrate in the first circuit area is located at a lower level than a second device forming surface of the substrate in the second circuit area as viewed in cross section,
• a memory cell forming surface of the substrate in the memory cell area is located at a same level as or at a lower level than the first device forming surface of the substrate in the first circuit area as viewed in cross section, and
• device forming surfaces of the substrate in the second, third, fourth and fifth circuit area are located at a same level and at a higher level than the first device forming surface.