Transient voltage suppression device with improved electrostatic discharge (esd) robustness

A transient voltage suppression device with improved electrostatic discharge (ESD) robustness comprising:

• a semiconductor substrate having a first conductivity type;
• a first doped well having a second conductivity type, arranged in the semiconductor substrate, and spaced from a bottom of the semiconductor substrate;
• a first heavily-doped area having the first conductivity type and arranged in the first doped well;
• a second doped well having the second conductivity type, arranged in the semiconductor substrate, and spaced from the bottom of the semiconductor substrate;
• a second heavily-doped area having the first conductivity type and arranged in the second doped well;
• and
• a first current blocking structure arranged in the semiconductor substrate, spaced from the bottom of the semiconductor substrate and arranged between the first doped well and the second doped well, a depth of the first current blocking structure is deeper than or equal to depths of the first doped well and the second doped well, the first heavily-doped area and the second heavily-doped area are respectively electrically connected to a first pin and a second pin, the first current blocking structure is electrically floating, and when an electrostatic discharge (ESD) voltage is applied across the first pin and the second pin, a first electrostatic discharge (ESD) current flows from the first pin to the second pin and flows under the first current blocking structure.