Layout pattern for static random access memory

A static random access memory (SRAM) layout pattern, comprising:

• a substrate;
• two SRAM cells are disposed on the substrate, disposed in a first region and a second region adjacent to the first region respectively, wherein each SRAM cell includes a first inverter and a second inverter coupling with each other and constituting a latch circuit, wherein the first inverter includes a first pull-up transistor (PU1) and a first pull-down transistor (PD1), the second inverter includes a second pull-up transistor (PU2) and a second pull-down transistor (PD2);
• a first dummy gate layer located in the first region and crossing over a first fin structure;
• a second dummy gate layer located in the second region adjacent to the first dummy gate layer and crossing over a second fin structure, wherein the first fin structure directly contacts the second fin structure;
• and
• a contact structure disposed on the first dummy layer and electrically connected to a voltage source Vss.