Connection structure for stacked substrates

An integrated chip, comprising:

• a plurality of conductive interconnect layers disposed on a first surface of a first semiconductor substrate;
• and
• an interconnecting structure disposed inside the first semiconductor substrate and electrically coupled to the plurality of conductive interconnect layers, wherein the interconnecting structure comprises a first conductive layer and a second conductive layer disposed on the first conductive layer with a different pattern than the first conductive layer.

An integrated chip, comprising:

• a semiconductor substrate;
• and
• an interconnecting structure disposed within the semiconductor substrate and comprising a first conductive segment and a second conductive segment protruding outward from a bottom of the first conductive segment, wherein the first conductive segment is directly between sidewalls of the semiconductor substrate and laterally extends past an outermost sidewall of the second conductive segment.