US 2020/0027852 A1 · MULTI-CHIP INTEGRATED FAN-OUT PACKAGE

Abstract

A method includes surrounding a die and a conductive pillar proximate the die with a molding material, where the die and the conductive pillar are disposed over a first side of a first redistribution structure, where a second side of the first redistribution structure opposing the first side is attached to a first carrier; bonding conductive pads disposed on a first surface of a pre-made second redistribution structure to the die and to the conductive pillar, where a second surface of the pre-made second redistribution structure opposing the first surface is attached to a second carrier; after bonding the conductive pads, removing the second carrier to expose conductive features of the pre-made second redistribution structure proximate the second surface; and forming conductive bumps over and electrically coupled to the conductive features of the pre-made second redistribution structure.

Claims20

Dependent claims

A semiconductor package comprising:

a die and a first conductive pillar adjacent to the die, the die having die connectors at a front side of the die;
a molding material around the die and the first conductive pillar;
a first redistribution structure extending along a backside of the die and electrically coupled to the first conductive pillar;
and
a second redistribution structure extending along the front side of the die, wherein the second redistribution structure is electrically coupled to the first conductive pillar and first ones of the die connectors, and wherein the second redistribution structure has a second width different from a first width of the first redistribution structure.

2 more elements

Dependencies are inferred from the claim text.

Multi-chip integrated fan-out package

Life of this patent

Multi-chip integrated fan-out package

Life of this patent

Abstract

Claims20