Maintaining height of alignment key in semiconductor devices

A semiconductor device, comprising:

• a conductive structure disposed on a substrate;
• a capping structure covering an upper surface of the conductive structure, the capping structure comprising:
• a capping pattern containing silicon oxycarbide (SiOC);
• and
• a first etch stop pattern covering a lower surface and a sidewall of the capping pattern, the first etch stop pattern containing a material, which has a first etching selectivity with respect to the capping pattern;
• an alignment key on the substrate, the alignment key containing a material having a second etching selectivity lower than the first etching selectivity with respect to the capping pattern;
• and
• a filling structure disposed on the substrate, the filling structure covering a sidewall of the alignment key, and the filling structure comprising:
• a first filling pattern;
• a second filling pattern covering a lower surface and a sidewall of the first filling pattern, the second filling pattern and the capping pattern containing a same material;
• and
• a second etch stop pattern covering a lower surface and a sidewall of the second filling pattern, the first etch stop pattern and the second etch stop pattern containing a same material.

A semiconductor device, comprising:

• an active region disposed on a substrate, the active region defined by an isolation pattern on the substrate;
• a gate electrode structure disposed on the active region and the isolation pattern;
• a capping structure covering an upper surface of the gate electrode structure, the capping structure comprising:
• a capping pattern containing silicon oxycarbide (SiOC);
• and
• an etch stop pattern covering a lower surface and a sidewall of the capping pattern, the etch stop pattern containing a material, the material comprising silicon nitride (SiN), silicon oxynitride (SiON) or silicon carbonitride (SiCN);
• and
• a source/drain layer on the active region adjacent to the gate electrode structure.