Via-Configurable Memory
AssigneeIntel Corporation
InventorsWayson Lowe, Ban Pak Wong
Life of this patent
Estimating the term…
Abstract
An integrated circuit device includes a memory circuit and a via layer that are used to support different memory demands based on a via configuration of the via layer. A first via configuration of the via layer causes the memory circuit of the integrated circuit device to function as a true dual-port memory circuit in a first via configuration. Moreover, a second via configuration of the via layer causes the memory circuit of the integrated circuit device to function as a simple dual-port memory circuit in a second via configuration.
Claims20
An integrated circuit device comprising:
- a memory circuit;
- and
- a via layer that, based on a via configuration of the via layer, causes the memory circuit of the integrated circuit device to function as:
- a true dual-port memory circuit in a first via configuration;
- and
- a simple dual-port memory circuit in a second via configuration.
A method of manufacturing an integrated circuit comprising:
- forming memory circuitry using a first one or more masks;
- and
- forming vias using a second one or more masks to produce one of a plurality of via configurations, wherein a first via configuration of the plurality of via configurations causes a portion of the memory circuitry to operate as a first bit width memory circuit, wherein a second via configuration of the plurality of via configurations causes a portion of the memory circuitry to operate as a second bit width memory circuit, and wherein the first bit width and the second bit width are different.
A configurable circuit, comprising:
- a memory circuit comprising an array of memory cells, a plurality of multiplexers, one or more row decoders, one or more column decoders, one or more bit lines, one or more word lines, or a combination thereof;
- and
- a plurality of vias connected to at least a portion of the memory circuit to implement:
- a true dual-port memory circuit in a first via configuration;
- a simple dual-port memory circuit in a second via configuration;
- a first bit width memory circuit in a third via configuration;
- and
- a second bit width memory circuit in a fourth configuration.
Dependencies are inferred from the claim text.