Packaged integrated circuit having stacked die and method for therefor

A packaged integrated circuit (IC) device comprising:

• a first set of stacked dies including:
• a first IC die,
• a first inductor in the first IC die,
• an isolation layer over the first IC die,
• a second IC die over the isolation layer, and
• a second inductor in the second IC die aligned to communicate with the first inductor, wherein the isolation layer extends a prespecified distance beyond a first edge of the second IC die;
• and
• a second set of stacked dies including:
• a third IC die,
• a third inductor in the third IC die,
• a second isolation layer over the third IC die,
• a fourth IC die over the second isolation layer, and
• a fourth inductor in the fourth IC die aligned to communicate with the third inductor, wherein the second isolation layer extends a second prespecified distance beyond a first edge of the fourth IC die,
• wherein the first IC die and third IC die are in separate high voltage domains, and the second IC die and the fourth IC die are in a separate low voltage domain, wherein each of the high voltage domains operate at higher voltages than the low voltage domain.

A packaged integrated circuit (IC) device comprising:

• a first set of stacked die including:
• a first IC die,
• a first inductor in the first IC die,
• an isolation layer over the first IC die,
• a second IC die over the isolation layer,
• a second inductor in the second IC die aligned to communicate with the first inductor, wherein the isolation layer extends a prespecified distance beyond a first edge of the second IC die, and
• a conductive ring between isolation layer and the second IC die, the conducive ring extending past the first edge of the second IC die, wherein the first edge is perpendicular to the isolation layer;
• and
• a second set of stacked die including:
• a third IC die,
• a third inductor in the third IC die,
• a second isolation layer over the third IC die,
• a fourth IC die over the second isolation layer, and
• a fourth inductor in the fourth IC die aligned to communicate with the third inductor, wherein the second isolation layer extends a second prespecified distance beyond a first edge of the fourth IC die.