Test structure for inline detection of interlayer metal defects
AssigneeQUALCOMM Incorporated
InventorsFadoua CHAFIK, Samit SENGUPTA
Life of this patent
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Abstract
A integrated circuit structure has a first test structure with a first set of un-landed vias. The first set of un-landed vias has a first side for each of the first set of un-landed vias proximate to a first BEOL layer (first back-end-of-line layer) of a chip and spaced apart, by a first gap, from the first BEOL layer. Each of the first set of un-landed vias has a first depth that is smaller than a landed depth of a chip via conductively connecting the first BEOL layer to a second BEOL layer of the chip. The first set of un-landed vias also has a second side for each of the first set of un-landed vias opposite the first side and connected to the second BEOL layer.
Claims20
A integrated circuit structure, comprising:
- a first test structure comprising,
- a first set of un-landed vias comprising:
- a first side for each of the first set of un-landed vias proximate to a first BEOL layer (first back-end-of-line layer) of a chip and spaced apart, by a first gap, from the first BEOL layer, in which each of the first set of un-landed vias has a first depth that is smaller than a landed depth of a chip via conductively connecting the first BEOL layer to a second BEOL layer of the chip;
- and
- a second side for each of the first set of un-landed vias opposite the first side and connected to the second BEOL layer.
A method of making an integrated circuit structure, comprising:
- fabricating a first set of landed vias between and connecting a first back-end-of-line (BEOL) layer and a second BEOL layer, each of the first set of landed vias having a landed depth;
- and
- fabricating a first test structure including a first set of un-landed vias proximate, but not contacting the first BEOL layer, in which each of the first set of un-landed vias has a first depth that is smaller than the landed depth of a chip via, the first set of un-landed vias connected to the second BEOL layer.
A integrated circuit structure, comprising:
- a first test structure comprising,
- means for shorting a first BEOL layer (first back-end-of-line layer) of a chip and a second BEOL layer in the presence of a latent defect, each of the shorting means comprising;
- a first side proximate the first BEOL layer and spaced apart, by a first gap, from the first BEOL layer,
- a first depth that is smaller than a landed depth of a chip via conductively connecting the first BEOL layer to the second BEOL layer of the chip;
- and
- a second side opposite the first side and connected to the second BEOL layer;
- and
- a second test structure comprising a set of un-landed vias comprising:
- a third side for each of the set of un-landed vias proximate to the first BEOL layer and spaced apart, by a second gap, from the first BEOL layer, in which each of the set of un-landed vias has a second depth that is smaller than the landed depth of the chip via;
- and
- a fourth side for each of the set of un-landed vias opposite the third side and connected to the second BEOL layer, the first depth different from the second depth and a dimension of the first gap different from a dimension of the second gap.
A radio frequency (RF) front end module comprising:
- an integrated circuit having a first test structure including a first side for each of a first set of un-landed vias proximate to a first BEOL layer (first back-end-of-line layer) of a chip and spaced apart, by a first gap, from the first BEOL layer, in which each of the first set of un-landed vias has a first depth that is smaller than a landed depth of a chip via conductively connecting the first BEOL layer to a second BEOL layer of the chip, and a second side for each of the first set of un-landed vias opposite the first side and connected to the second BEOL layer;
- and
- an antenna coupled to the integrated circuit.
Dependencies are inferred from the claim text.