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US 2020/0027800 A1Published application
Semiconductor memory and method of manufacturing the semiconductor memory
AssigneeToshiba Memory Corporation
InventorsNaoki YAMAMOTO, Yu HIROTSU
Life of this patent
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Abstract
A semiconductor memory according to an embodiment includes first and second areas, an active region, a non-active region, a first stacked body, a plurality of first pillars, a first contact, a second stacked body, and a second contact. The active region includes part of each of the first and second areas. The non-active region includes part of each of the first and second areas. The second stacked body is in the non-active region. The second stacked body includes second insulators and second conductors which are alternately stacked. A second contact is in contact with a second conductor in a first interconnect layer and a second conductor in a second interconnect layer.
Claims20
A semiconductor memory comprising:
- first and second areas arranged in a first direction;
- an active region including part of each of the first and second areas;
- a non-active region including part of each of the first and second areas;
- a first stacked body in the active region, the first stacked body including first insulators and first conductors which are alternately stacked, each of the first conductors including a terraced portion that does not overlap the upper first conductor in the second area;
- a plurality of first pillars each penetrating the first stacked body in the first area, an intersection between the first pillar and the first conductor functions as a memory cell;
- a first contact on a terraced portion of a first conductor in a first interconnect layer;
- a second stacked body in the non-active region, the second stacked body including second insulators and second conductors which are alternately stacked, each of the second conductors including a terraced portion that does not overlap the upper second conductor in the second area;
- and
- a second contact that is in contact with a second conductor in the first interconnect layer and a second conductor in a second interconnect layer different from the first interconnect layer.
6 more elements
A semiconductor memory comprising:
- first and second areas arranged in a first direction;
- an active region including part of each of the first and second areas;
- a non-active region including part of each of the first and second areas;
- a first stacked body in the active region, the first stacked body including first insulators and first conductors which are alternately stacked, each of the first conductors including a terraced portion that does not overlap the upper first conductor in the second area;
- a plurality of first pillars each penetrating the first stacked body in the first area, an intersection between the first pillar and the first conductor functions as a memory cell;
- a first contact on a terraced portion of a first conductor in a first interconnect layer;
- a second stacked body in the non-active region, the second stacked body including second insulators and second conductors which are alternately stacked, each of the second conductors including a terraced portion that does not overlap the upper second conductor in the second area;
- and
- a second contact that is in contact with at least one of the second conductors in the second area,
- wherein:
- the first contact and the second contact are each provided like a pillar;
- and
- an outside diameter of the second contact is larger than an outside diameter of the first contact in a section parallel to a surface of a substrate.
10 more elements
A method of manufacturing a semiconductor memory, comprising:
- forming a first stacked body and a second stacked body, the first stacked body including first conductors and first insulators which are alternately stacked, each of the first conductors having a terraced portion that does not overlap the upper first conductor in an end portion area thereof, the second stacked body including second conductors and second insulators which are alternately stacked, each of the second conductors having a terraced portion that does not overlap the upper second conductor in an end portion area thereof;
- forming a first hole and a second hole, the first hole being formed to expose a terraced portion of a first conductor in a first interconnect layer, the second hole being formed to expose a terraced portion of a second conductor in the first interconnect layer and a terraced portion of a second conductor in a second interconnect layer different from the first interconnect layer;
- measuring an amount of overlay shift of the second hole based on a shape of the second hole and a boundary between adjacent terraced portions exposed to a bottom of the second hole;
- and
- forming a contact in the first hole after the measuring.
2 more elements
Dependencies are inferred from the claim text.