Controlling active fin height of finfet device using etch protection layer to prevent recess of isolation layer during gate oxide removal

A semiconductor device, comprising:

• first and second vertical semiconductor fins disposed on a semiconductor substrate, the first and second vertical semiconductor fins each comprising a first fin portion having a first width, and a second fin portion having a second width, wherein the second width is less than the first width;
• an isolation layer disposed on the semiconductor substrate, wherein the isolation layer covers the first fin portions, and wherein the second fin portions extend above a surface of the isolation layer;
• a first fin field-effect transistor device comprising the second fin portion of the first vertical semiconductor fin, and a first gate structure which overlaps a portion of the second fin portion of the first vertical semiconductor fin in a first gate region of the first fin field-effect transistor device, wherein the first gate structure comprises a high-k metal gate structure;
• and
• a second fin field-effect transistor device comprising the second fin portion of the second vertical semiconductor fin, and a second gate structure which overlaps a portion of the second fin portion of the second vertical semiconductor fin in a second gate region of the second fin field-effect transistor device, wherein the second gate structure comprises a gate oxide layer disposed on the second fin portion of the second vertical semiconductor fin;
• wherein the isolation layer prevents the first and second gate structures from being formed in contact with sidewalk of the first fin portions of the respective first and second vertical semiconductor fins.

A semiconductor device, comprising:

• a vertical semiconductor fin disposed on a semiconductor substrate, the vertical semiconductor fin comprising a first fin portion having a first width, and a second fin portion having a second width, wherein the second width is less than the first width;
• an isolation layer disposed on the semiconductor substrate, wherein the isolation layer covers the first fin portion, and wherein the second fin portion extends above a surface of the isolation layer;
• and
• a fin field-effect transistor device comprising the second fin portion of the vertical semiconductor fin, a gate structure which overlaps a portion of the second fin portion of the vertical semiconductor fin, and source/drain layers formed on exposed portions of the second fin portion of the vertical semiconductor fin which extend from the gate structure on opposing sides of the gate structure;
• wherein the isolation layer prevents the gate structure from being formed in contact with sidewalls of the first fin portion of the vertical semiconductor fin.