Gate spacer formation for scaled cmos devices

A method of forming a CMOS device, comprising:

• providing a dummy gate structure atop a substrate;
• forming a first spacer over the dummy gate structure;
• removing the first spacer from just an upper portion of the dummy gate structure by performing an angled reactive ion etch disposed at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate;
• and
• forming a second spacer over the upper portion of the dummy gate structure and over the first spacer along a lower portion of the dummy gate structure, wherein a thickness of the first spacer and the second spacer along the lower portion of the dummy gate structure is greater than a thickness of the second spacer along the upper portion of the dummy gate structure.

A method of forming a CMOS device, comprising:

• providing a dummy gate structure atop a substrate;
• forming a first gate spacer over the dummy gate structure, wherein the first gate spacer extends along an upper surface of the substrate;
• removing the first spacer from just an upper portion of the dummy gate structure by performing an angled reactive ion etch disposed at a non-zero angle of inclination with respect to a perpendicular to a plane of the upper surface of the substrate;
• and
• forming a second gate spacer over the upper portion of the dummy gate structure and over the first gate spacer along a lower portion of the dummy gate structure, wherein a thickness of the first gate spacer and the second gate spacer along the lower portion of the dummy gate structure is greater than a thickness of the second gate spacer along the upper portion of the dummy gate structure.