US 2020/0027791 A1Published application

Optimizing Junctions of Gate All Around Structures with Channel Pull Back

AssigneesInternational Business Machines Corporation, Commissariat A L'energie Atomique Et Aux Energies Alternatives

InventorsNicolas Loubet, Emmanuel Augendre, Remi Coquand, Shay Reboh

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Abstract

Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.

Claims22

Dependent claims

A method of forming a nanosheet device, the method comprising the steps of:

forming an alternating series of first nanosheets comprising a first material and second nanosheets comprising a second material as a stack on a wafer;
forming at least one dummy gate on the stack;
forming spacers along opposite sidewalls of the at least one dummy gate;
patterning the stack into at least one fin stack beneath the at least one dummy gate;
etching the at least one fin stack to selectively pull back the second nanosheets in the at least one fin stack forming pockets in the at least one fin stack;
filling the pockets with a strain-inducing material;
forming source and drains on opposite sides of the at least one fin stack;
burying the at least one dummy gate in a dielectric material;
selectively removing the at least one dummy gate forming at least one gate trench in the dielectric material;
selectively removing, through the at least one gate trench, either the first nanosheets or the second nanosheets from the at least one fin stack;
and
forming at least one replacement gate in the at least one gate trench.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/038,985Filed 18 Jul 2018
Published: 23 Jan 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification33 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
B82Y 10/00
Nanotechnology for information processing, storage or transmission
H10D 30/019
Manufacture or treatment: of FETs having stacked nanowire, nanosheet or nanoribbon channels
H10D 30/0243
Of fin field-effect transistors [FinFET]: using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide…