Inductor structure for integrated circuit

An integrated chip, comprising:

• a first plurality of conductive interconnect layers disposed within a first inter-level dielectric (ILD) structure on a first surface of a first substrate;
• one or more redistribution layers disposed within one or more dielectric structures on a second surface of the first substrate that opposes the first surface;
• a bond pad coupled to the one or more redistribution layers, wherein the one or more redistribution layers are vertically between the bond pad and the first substrate;
• a plurality of through-substrate-vias (TSVs) extending through the first substrate and coupling the first plurality of conductive interconnect layers to the one or more redistribution layers;
• and
• wherein the one or more redistribution layers define at least a part of an inductor having one or more turns that wind around an axis.

An integrated chip, comprising:

• a first plurality of conductive routing layers disposed within a first dielectric structure along a first surface of a first substrate;
• a second plurality of conductive routing layers disposed within a second dielectric structure along a second surface of the first substrate opposing the first surface;
• a passivation layer disposed on the second surface of the first substrate and separating the second plurality of conductive routing layers from the first substrate;
• a plurality of through-substrate-vias (TSVs) extending through the first substrate and coupling the first plurality of conductive routing layers to the second plurality of conductive routing layers;
• and
• wherein the first plurality of conductive routing layers, the second plurality of conductive routing layers, or the plurality of TSVs define an inductor having one or more turns that wind around an axis extending in parallel to the first surface of the first substrate.