Etch-stop layer topography for advanced integrated circuit structure fabrication

An integrated circuit structure, comprising:

• a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate, individual ones of the plurality of conductive interconnect lines having an upper surface below an upper surface of the ILD layer;
• an etch-stop layer on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines;
• and
• a conductive via on and electrically coupled to an individual one of the plurality of conductive interconnect lines, the conductive via in an opening of the etch-stop layer.

An integrated circuit structure, comprising:

• a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate, individual ones of the plurality of conductive interconnect lines having an upper surface above an upper surface of the ILD layer;
• an etch-stop layer on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with a lowermost portion of the non-planar upper surface over the ILD layer and an uppermost portion of the non-planar upper surface over the plurality of conductive interconnect lines;
• and
• a conductive via on and electrically coupled to an individual one of the plurality of conductive interconnect lines, the conductive via in an opening of the etch-stop layer.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate, individual ones of the plurality of conductive interconnect lines having an upper surface below an upper surface of the ILD layer;
• an etch-stop layer on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines;
• and
• a conductive via on and electrically coupled to an individual one of the plurality of conductive interconnect lines, the conductive via in an opening of the etch-stop layer.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate, individual ones of the plurality of conductive interconnect lines having an upper surface above an upper surface of the ILD layer;
• an etch-stop layer on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with a lowermost portion of the non-planar upper surface over the ILD layer and an uppermost portion of the non-planar upper surface over the plurality of conductive interconnect lines;
• and
• a conductive via on and electrically coupled to an individual one of the plurality of conductive interconnect lines, the conductive via in an opening of the etch-stop layer.