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US 2020/0027737 A1Published application
Plating interconnect for silicon chip
AssigneeTexas Instruments Incorporated
InventorsJerard Canuto Malado, Antonio Rosario Taloban, JR.
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Abstract
A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads.
Claims9
A method for forming interconnections between a silicon die and external leads of a silicon chip package comprising:
- forming a pre-mold onto a front assembly of the silicon chip package, wherein the silicon die is disposed on the front assembly;
- etching a trace pattern on the pre-mold, wherein the trace pattern is representative of the interconnections;
- plating rigid traces onto the trace pattern;
- and
- molding the silicon chip package.
2 more elements
Dependencies are inferred from the claim text.