Varying Temperature Anneal for Film and Structures Formed Thereby
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShu Ling Liao, Chung-Chi Ko, Wan-Yi Kao
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Abstract
Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.
Claims20
A semiconductor structure comprising:
- an active area on a substrate, the active area comprising a source/drain region;
- a gate structure over the active area;
- and
- a gate spacer along a sidewall of the gate structure, the gate spacer being disposed laterally between the gate structure and the source/drain region, the gate spacer comprising:
- a first spacer layer;
- and
- a second spacer layer formed over the first spacer layer, wherein the second spacer layer has a carbon concentration in a range from 0 atomic percent (at. %) to 5 at. %, and the second spacer layer has a lower k-value than the first spacer layer.
A semiconductor structure comprising:
- a gate structure over a semiconductor substrate;
- and
- a first gate spacer along a sidewall of the gate structure;
- and
- a second gate spacer along a sidewall of the first gate spacer, wherein the first gate spacer completely separates the second gate spacer from the gate structure, wherein the second gate spacer has a carbon concentration in a range from 0 atomic percent (at. %) to 5 at. %, and the second gate spacer has a lower k-value than the first gate spacer.
A semiconductor structure comprising:
- a gate structure over a semiconductor substrate;
- and
- a first gate spacer along a sidewall of the gate structure, wherein the first gate spacer has a carbon concentration in a range from 0 atomic percent (at. %) to 5 at. %, wherein the first gate spacer comprises oxygen in a range from about 40 at. % to about 70 at. %., wherein the first gate spacer comprises silicon of about 65.3 at. %, wherein the first gate spacer has a dielectric constant less than 4.1, and wherein the first gate spacer comprises nitrogen in a range from about 0 at. % to about 15 at. %.
Dependencies are inferred from the claim text.