Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformity

A method of semiconductor device fabrication, comprising:

• determining a pattern density (PD) target having a second range of pattern densities;
• based on the PD target and the second range of pattern densities, identifying, a first template having a first layout pattern with a first PD and a second template having a second layout pattern with a second PD different than the first PD;
• splitting the first template into a plurality of subset templates, wherein each subset template of the plurality of subset templates includes a portion of the first layout pattern and a percentage of the first PD, and wherein a first subset template has a subset PD that is outside of the PD target;
• inserting a sub-resolution dummy feature into the portion of the layout pattern defined by the first subset template and the second template;
• and
• performing an electron beam (e-beam) lithography exposure process with an e-beam lithography tool to a semiconductor substrate, using respective ones of the plurality of subset templates.

A method of semiconductor device fabrication, comprising:

• based on a pattern density (PD) target, identifying a first template including a first layout pattern with a first PD and a second template including a second layout pattern with a second PD less than the first PD;
• splitting the first template into a plurality of subset templates including at least a first subset template and a second subset template;
• performing a PD uniformity (PDU) optimization to the second template and to the second subset template;
• and
• performing an e-beam lithography exposure process with an e-beam lithography tool to a semiconductor substrate using the first and second subset templates.