Memory device and memory peripheral circuit

A memory peripheral circuit, coupled to a memory array, the memory peripheral circuit comprising:

• a redundancy column data circuit, configured to store redundancy column information and provide a redundancy test mode data signal and a column address signal according to the redundancy column information, wherein the column address signal comprises a redundancy column address signal;
• and
• a column selection control circuit, coupled between the redundancy column data circuit and the memory array, and configured to receive the redundancy test mode data signal and the column address signal, wherein the column selection control circuit comprises:
• a column decoder, coupled between a main memory block of the memory array and the redundancy column data circuit, and configured to disable a bad column address of the main memory block according to the redundancy test mode data signal and the redundancy column address signal;
• and
• a redundancy column decoder, coupled between a redundancy memory block of the memory array and the redundancy column data circuit, and configured to latch the redundancy column address signal according to the redundancy test mode data signal, compare the column address signal with the latched redundancy column address signal to obtain a comparison result and enable a redundancy column address of the redundancy memory block according to the comparison result.