Stacked memory devices, memory systems and methods of operating stacked memory devices

A memory system comprising:

• a memory controller configured to control a stacked memory device;
• and
• the stacked memory device, the stacked memory device including,
• a buffer die configured to communicate with the memory controller, the buffer die including a test circuit;
• a plurality of memory dies stacked on the buffer die, each of the plurality of memory dies including a memory cell array, the memory cell array including a plurality of dynamic memory cells coupled to a plurality of word-lines and a plurality of bit-lines;
• and
• a plurality of through silicon vias (TSVs) extending through the plurality of memory dies to connect to the buffer die;
• and
• the test circuit, during a test mode of the stacked memory device is configured to in response to test command or a test mode register set (TMRS) from the memory controller,
• perform a test on the dynamic memory cells of a target memory die corresponding to at least one of the plurality of memory dies, the test to detect at least one defective cell of the target memory die, and
• store, as fail address information, an address of a memory cell row including the at least one defective cell detected through the test, in at least one column decoder of another memory die of the plurality of memory dies, the another memory die not being the target memory die.

A method of operating a stacked memory device, the stacked memory device including a buffer die that communicates with at least one external device, a plurality of memory dies stacked on the buffer die, and a plurality of through silicon vias (TSVs) extending through the plurality of memory dies to connect to the buffer die, the method comprising:

• performing a test on dynamic memory cells of a target memory die corresponding to one of the plurality of memory dies, the test to detect at least one defective cell of the target memory die;
• temporarily storing a fail address in a column decoder of the target memory die based on results of the test of the target memory die;
• storing the fail address in at least one column decoder of another memory die of the plurality of memory dies, the another memory die not being the target memory die;
• and
• transmitting the fail address to the external device from the at least one column decoder of the another memory die through a data input/output path of the stacked memory device.