Semiconductor storage device

A semiconductor storage device comprising:

• a first semiconductor extending above a substrate and including a first part that extends above the substrate and a second part that extends above the substrate;
• a first word line at a first level above the substrate and facing the first part of the first semiconductor;
• a second word line at the first level above the substrate and facing the second part of the first semiconductor, such that the first semiconductor is between the second word line and the first word line, and the second word line is separate from the first word line;
• a first cell transistor including a first area of the first part of the first semiconductor that faces the first word line;
• and
• a second cell transistor including a second area of the second part of the first semiconductor that faces the second word line, the second cell transistor storing data which is the same as data stored in the first cell transistor,
• wherein a first voltage is applied to the first word line and the second word line during an operation of reading data from the first cell transistor.

A semiconductor storage device comprising:

• a plurality of semiconductor pillars each extending above a substrate;
• a first bit line electrically connected to a first semiconductor pillar of the plurality of semiconductor pillars;
• a second bit line electrically connected to a second semiconductor pillar of the plurality of semiconductor pillars;
• a third bit line electrically connected to a third semiconductor pillar of the plurality of semiconductor pillars;
• a first word line at a first level above the substrate;
• a second word line at the first level above the substrate and electrically isolated from the first word line;
• a first cell transistor including a first part of the first semiconductor pillar that faces the first word line;
• a second cell transistor including a second part of the first semiconductor pillar that faces the second word line;
• a third cell transistor including a first part of the second semiconductor pillar that faces the first word line;
• a fourth cell transistor including a second part of the second semiconductor pillar that faces the second word line;
• a fifth cell transistor including a first part of the third semiconductor pillar that faces the first word line;
• a sixth cell transistor including a second part of the third semiconductor pillar that faces the second word line;
• a first select transistor between the first bit line and the first cell transistor;
• a second select transistor between the first bit line and the second cell transistor;
• a third select transistor between the second bit line and the third cell transistor;
• a fourth select transistor between the second bit line and the fourth cell transistor;
• a fifth select transistor between the third bit line and the fifth cell transistor;
• a sixth select transistor between the third bit line and the sixth cell transistor, wherein
• the first, third, and fifth select transistors are commonly controlled to be ON or OFF, and the fourth and sixth select transistors are commonly controlled to be ON or OFF, and
• during a reading operation to read data from the first cell transistor, the first, third, and fifth select transistors are controlled to be ON, and the second, fourth, and sixth select transistors are controlled to be OFF, and a first voltage that is greater than or equal to zero voltage and less than a threshold voltage of the second cell transistor is applied to the second word line.