Novel resistive random access memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Fu LEE, Yu-Der CHIH
Life of this patent
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Abstract
A memory device includes: a memory bit cell; a write circuit, coupled to the memory bit cell, and configured to use a first voltage to transition the memory bit cell to a first logic state by changing a respective resistance state of the memory bit cell, and compare a first current flowing through the memory bit cell with a first reference current; and a control logic circuit, coupled to the write circuit, and configured to determine whether the first logic state is successfully written into the memory bit cell based on a read-out logic state of the memory bit cell and the comparison between the first current and first reference current.
Claims20
A memory device, comprising:
- a memory bit cell;
- a write circuit, coupled to the memory bit cell, and configured to use a first voltage to transition the memory bit cell to a first logic state by changing a respective resistance state of the memory bit cell, and compare a first current flowing through the memory bit cell with a first reference current;
- and
- a control logic circuit, coupled to the write circuit, and configured to determine whether the first logic state is successfully written into the memory bit cell based on a read-out logic state of the memory bit cell and the comparison between the first current and first reference current,
- wherein when the write circuit determines that the first current is lower than the first reference current, the control logic circuit further causes the write circuit to use a third voltage to transition the memory bit cell still to the first logic state, and compare a third current flowing through the memory bit cell with a third reference current, and wherein the third voltage is higher than the first voltage, and the third reference current is higher than the first reference current.
A method, comprising:
- providing a first voltage to transition a memory bit cell to a first logic state by changing a respective resistance state of the memory bit cell;
- comparing a first current flowing through the memory bit cell with a first reference current;
- and
- monitoring the comparison between the first current and first reference current, and a read-out logic state of the memory bit cell to determine whether the first logic state is successfully written into the memory bit cell, wherein when the first current is lower than the first reference current, the method further comprises:
- providing a third voltage to transition the memory bit cell still to the first logic state;
- and
- comparing a third current flowing through the memory bit cell with a third reference current, wherein the third voltage is higher than the first voltage, and the third reference current is higher than the first reference current.
A method, comprising:
- providing a first voltage to transition a memory bit cell to a first logic state;
- comparing a first current corresponding to the first voltage and flowing through the memory bit cell with a first reference current;
- when the first current is higher than the first reference current, comparing a read-out logic state of the memory bit cell with the first logic state to determine whether to cease providing the first voltage to the memory bit cell or to provide a second voltage to transition the memory bit cell still to the first logic state;
- and
- when the first current is lower than the first reference current, providing a third voltage to transition the memory bit cell still to the first logic state, and comparing a third current corresponding to the third voltage and flowing through the memory bit cell with a third reference current, wherein the second voltage and the third voltage are different from the first voltage, and wherein when the read-out logic state is not consistent with the first logic state, the method further comprises:
- providing a second voltage to transition the memory bit cell still to the first logic state, and
- comparing a second current flowing through the memory bit cell with a second reference current.
Dependencies are inferred from the claim text.