Serialized sram access to reduce congestion
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsin-Cheng Chen, Jack Liu
Life of this patent
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Abstract
A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input signals each having a second bit-width. A memory array is configured to receive each of the plurality of serialized input signals. The memory array is further configured to generate a plurality of serialized output signals. A de-serializer is configured to receive the plurality of serialized output signals and generate a non-serialized output signal. The plurality of serialized output signals each have a bit-width equal to second bit-width and the non-serialized output signal has a bit-width equal to the first bit-width.
Claims20
A circuit, comprising:
- a plurality of columns each comprising:
- a plurality of bit-cells each electrically coupled to one of a plurality of bit-lines;
- a multiplexer electrically coupled to each of the plurality of bit-lines, wherein the multiplexer is configured to select one of the plurality of bit-lines;
- a sensing amplifier electrically coupled to the multiplexer, wherein the sensing amplifier is configured to generate a bit-output based on the selected one of the plurality of bit-lines;
- a row decoder configured to generate one or more control signals for each of the plurality of columns in response to an address signal;
- and
- a flip-flop configured to receive one or more address signals and generate one or more bit-selection signals for the row decoder and the multiplexer in each of the plurality of columns.
A method, comprising:
- receiving a first address signal;
- initiating a first serialized operation at a first memory array;
- receiving a second address signal;
- initiating a second serialized operation at a second memory array.
A circuit, comprising:
- a plurality of columns each comprising:
- a plurality of bit-cells each electrically coupled to one of a plurality of bit-lines;
- a multiplexer electrically coupled to each of the plurality of bit-lines, wherein the multiplexer is configured to select one of the plurality of bit-lines;
- a sensing amplifier electrically coupled to the multiplexer, wherein the sensing amplifier is configured to generate a bit-output based on the selected one of the plurality of bit-lines;
- a row decoder configured to generate one or more control signals for each of the plurality of columns in response to an address signal;
- a plurality of bit-specific flip-flops each configured to receive a respective bit of a serialized input signal and generate a bit-specific output;
- and
- a bit-line write decoder coupled to each of the plurality of bit-specific flip-flops, wherein the bit-line write decoder is configured to latch each of the bit-specific outputs, and wherein the bit-line write decoder is configured to generate a first plurality of bit-cell write signals and a second plurality of bit-cell write signals.
Dependencies are inferred from the claim text.