Method and apparatus to reduce power consumption for refresh of memory devices on a memory module
AssigneeIntel Corporation
InventorsDouglas HEYMANN, Wei P. CHEN, Suresh CHITTOR, George VERGIS
Life of this patent
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Abstract
Power consumption for refresh of memory devices on a memory module is reduced by each memory device on the memory module to one of a plurality of sub channels on the memory module. Each sub channel has a thermal sensor that monitors the temperature of the DRAM chips in the region. The refresh rate is increased only for the memory devices in the sub channel in which the memory devices operate above a predefined high temperature. This results in a reduction in power required by the memory module for refresh and an increase in the maximum bandwidth of the memory module.
Claims20
A memory controller, comprising:
- a Dynamic Random Access Memory (DRAM) interface to transfer data over a bus to a memory module, the memory module comprising at least two sub channels, each sub channel comprising a plurality of DRAM devices;
- a first refresh mode register to store a first refresh rate for a first sub channel of the memory module;
- a second refresh mode register to store a second refresh rate for a second sub channel of the memory module;
- and
- a memory module refresh mode controller to modify the first refresh rate based a first temperature read from a first thermal sensor in the first sub channel and to modify the second refresh rate based on a second temperature read from a second thermal sensor in the first sub channel.
A method comprising:
- transferring, by a Dynamic Random Access Memory (DRAM) interface, data over a bus to a memory module, the memory module comprising at least two sub channels, each sub channel comprising a plurality of DRAM devices;
- storing, in a first refresh mode register, a first refresh rate for a first sub channel of the memory module;
- storing in a second refresh mode register, a second refresh rate for a second sub channel of the memory module;
- and
- modifying, by a memory module refresh mode controller, the first refresh rate based a first temperature read from a first thermal sensor in the first sub channel;
- and
- modifying, by the memory module refresh mode controller, the second refresh rate based on a second temperature read from a second thermal sensor in the first sub channel.
A system comprising:
- a memory module comprising at least two sub channels, each sub channel comprising a plurality of Dynamic Random Access Memory (DRAM) devices;
- a memory controller comprising:
- a DRAM interface to transfer data over a bus to the memory module;
- a first refresh mode register to store a first refresh rate for a first sub channel of the memory module;
- a second refresh mode register to store a second refresh rate for a second sub channel of the memory module;
- and
- a memory module refresh mode controller to modify the first refresh rate based a first temperature read from a first thermal sensor in the first sub channel and to modify the second refresh rate based on a second temperature read from a second thermal sensor in the first sub channel;
- and
- a display communicatively coupled to a processor to display data stored in the DRAM devices.
Dependencies are inferred from the claim text.