Semiconductor memory device and memory system having the same

A semiconductor memory device comprising:

• a data strobe signal input buffer configured to receive a data strobe signal and generate an input data strobe signal;
• a data input buffer configured to receive data, which is delayed by a first delay time compared to the data strobe signal, and generate input data;
• a latency control signal generator configured to generate a first on-die termination control signal and a second on-die termination control signal in response to receiving a write command, the latency control signal generator configured to activate the first on-die termination control signal during a first period in which the data strobe signal is applied, the latency control signal generator configured to activate the second on-die termination control signal during a second period in which the data is applied;
• a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal;
• a second on-die termination control circuit configured to vary a second variable resistance code in response to the second on-die termination control signal;
• a data strobe signal termination circuit configured to terminate the data strobe signal, the data strobe signal termination circuit including a first on-die termination resistor, the first on-die termination resistor configured to vary a resistance value thereof in response to the first variable resistance code;
• a data termination circuit configured to terminate the data, the data termination circuit including a second on-die termination resistor, the second on-die termination resistor configured to vary a resistance value thereof in response to the second variable resistance code;
• a row decoder configured to decode a row address signal and generate a plurality of word line selection signals;
• a column decoder configured to decode a column address signal and generate a plurality of column selection signals;
• and
• a memory cell array including a plurality of memory cells and configured to write the input data to the memory cells selected by the plurality of word line selection signals and the plurality of column selection signals.

A memory system comprising:

• a memory controller configured to transmit a first inverted chip selection signal and a second inverted chip selection signal;
• a first memory configured to be selected in response to the first inverted chip selection signal;
• and
• a second memory configured to be selected in response to the second inverted chip selection signal, each of the first and the second memories comprising,
• a data strobe signal input buffer configured to receive a data strobe signal transmitted from the memory controller, and generate an input data strobe signal,
• a data input buffer configured to receive data, which is delayed by a first delay time compared to the data strobe signal, and generate input data,
• a latency control signal generator configured to generate a first on-die termination control signal, which is activated during a first period in which the data strobe signal is applied, in response to receiving a write command,
• a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal,
• a data strobe signal termination circuit configured to terminate the data strobe signal, the data strobe signal termination circuit including a first on-die termination resistor, the first on-die termination resistor configured to vary a resistance value thereof in response to the first variable resistance code,
• a row decoder configured to decode a row address signal and generate a plurality of word line selection signals,
• a column decoder configured to decode a column address signal and generate a plurality of column selection signals, and
• a memory cell array including a plurality of memory cells and configured to write the input data to the memory cells selected by the plurality of word line selection signals and the column selection signals.