Systems and methods for controlling data strobe signals during read operations

An apparatus comprising:

• output buffer circuitry configured to provide a data strobe (DQS) signal to an output terminal responsive to a read clock signal;
• and
• control logic configured to selectively receive the read clock signal, and to:
• place, during a first period, the output buffer circuitry into an active state;
• hold, during a second period, the output buffer circuitry in the active state;
• and
• place, during a third period, the output buffer circuitry into an inactive state;
• wherein the output buffer circuitry, while in the active state, is configured to provide the DQS signal to the output terminal;
• wherein the control logic is configured to place the output buffer circuitry into the active state or inactive state in response to at least the read clock signal;
• and
• wherein the control logic is prevented from receiving the read clock signal during at least a portion of the second period.

A method, comprising:

• receiving, at output buffer circuitry, a read clock signal from a read clock generator;
• placing the output buffer circuitry in an active state during a first period in response to an activate signal from control logic, wherein the activate signal is responsive to the read clock signal;
• holding the output buffer circuitry in the active state during a second period;
• placing the output buffer circuitry in an inactive state during a third period in response to a deactivate signal from the control logic, wherein the deactivate signal is responsive to the read clock signal;
• passing a data strobe (DQS) signal, responsive to the read clock signal, from the output buffer circuitry to an output terminal while the output buffer circuitry is in the active state;
• and
• preventing the control logic from receiving the read clock signal during at least a portion of the second period.

An apparatus comprising:

• a clock generator;
• and
• a data strobe (DQS) generator, wherein the DQS generator further comprises:
• a DQS state control;
• and
• an output buffer;
• wherein the clock generator provides a read clock signal to the DQS generator, and wherein the DQS state control circuit selectively receives the read clock signal;
• wherein the DQS state control circuit selectively provides an activate signal to the output buffer responsive to at least the read clock signal, and
• wherein the output buffer selectively provides a DQS signal to an output terminal responsive to at least the read clock signal and the activate signal.