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US 2020/0027494 A1Published application
Memory device with a signal control mechanism
AssigneeMicron Technology, Inc.
InventorsAkira Yamashita, Kenji Asaki
Life of this patent
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Abstract
A memory device includes an internal storage unit configured to store mode data specifying an operating speed of the memory device; a control decoder coupled to the internal storage unit, the control decoder configured to generate a delay control signal based on the mode data; and an input buffer coupled to the control decoder, the input buffer configured to adjust a delay of an input signal based on the delay control signal.
Claims20
A memory device, comprising:
- an internal storage unit configured to store mode data corresponding to an operating speed of the memory device;
- a control decoder coupled to the internal storage unit, the control decoder configured to generate a delay control signal based on the mode data;
- and
- an input buffer coupled to the control decoder, the input buffer configured to adjust a delay of an input signal based on the delay control signal, wherein:
- the input signal is associated with a timing of a second signal, and
- the delay of the input signal is adjusted to maintain the timing when power levels associated with the input signal and the second signal differ.
3 more elements
A method of operating a memory device, the method comprising:
- determining an operating speed setting of the memory device;
- generating a delay control signal according to the operating speed setting;
- and
- controlling a delay of an input signal according to the delay control signal, wherein:
- the input signal is associated with a timing of a second signal, and
- the delay of the input signal is adjusted to maintain the timing when power levels associated with the input signal and the second signal differ.
3 more elements
Dependencies are inferred from the claim text.