US 2020/0027492 A1 · NON-VOLATILE MEMORY CELL, ARRAY AND FABRICATION METHOD

Abstract

The present invention provides a non-volatile memory cell, array and fabrication method. The memory cell comprises a substrate, a gate structure, a source region and a drain region, wherein the gate structure is formed on the substrate, the gate structure sequentially comprises a first gate dielectric layer, a first conductive layer, a second gate dielectric layer and a second conductive layer from bottom to top, the source region is formed in the substrate, the source region comprises an N-type heavily doped source region, the drain region is formed in the substrate, the drain region comprises an N-type doped drain region and a P-type heavily doped drain region formed in the N-type doped drain region. The non-volatile memory cell and array provided by the present invention have a band-to-band tunneling programming ability and reserve the advantage of high reading current of an N-channel at the same time.

Claims20

Dependent claims

A non-volatile memory cell, characterized in that the non-volatile memory cell comprises:

a substrate;
a gate structure formed on the substrate, wherein the gate structure sequentially comprises a first gate dielectric layer, a first conductive layer, a second gate dielectric layer and a second conductive layer from bottom to top;
a source region formed in the substrate, wherein the source region comprises an N-type heavily doped source region;
and
a drain region formed in the substrate, wherein the drain region comprises an N-type doped drain region and a P-type heavily doped drain region formed in the N-type doped drain region, wherein the source region and the drain region are respectively located at two ends of the gate structure, and the N-type doped drain region and the P-type heavily doped drain region both horizontally extend to positions below the gate structure and partially overlap with the gate structure.

2 more elements

A method for fabricating a non-volatile memory, characterized in that the method comprises the following steps:

providing a substrate;
forming a gate structure on the substrate, wherein the gate structure sequentially comprises a first gate dielectric layer, a first conductive layer, a second gate dielectric layer and a second conductive layer from bottom to top;
forming a source region in the substrate, wherein the source region comprises an N-type heavily doped source region;
and
forming a drain region in the substrate, wherein the drain region comprises an N-type doped drain region and a P-type heavily doped drain region formed in the N-type doped drain region, wherein the source region and the drain region are respectively located at two ends of the gate structure, and the N-type doped drain region and the P-type heavily doped drain region both horizontally extend to positions below the gate structure and partially overlap with the gate structure, respectively.

2 more elements

Dependencies are inferred from the claim text.

Non-volatile memory cell, array and fabrication method

Life of this patent

Non-volatile memory cell, array and fabrication method

Life of this patent

Abstract

Claims20