Back to results
US 2020/0027491 A1Published application
Memory cell, methods of forming and operating the same
AssigneeAgency for Science, Technology and Research
InventorsXuanyao Fong, Anh Tuan Do, Xin Liu
Life of this patent
Estimating the term…
Abstract
Various embodiments may provide a memory cell. The memory cell may include a magnetic tunneling junction memory including a first end and a second end. The memory cell may include a first transistor including a control electrode, a first controlled electrode and a second controlled electrode. The memory cell may also include a second transistor including a control electrode, a first controlled electrode and a second controlled electrode. The memory cell may additionally include a diode having a first end and a second end. In various embodiments, the memory cell may include a further magnetic tunneling junction memory, and a third transistor.
Claims20
A memory cell comprising:
- a magnetic tunneling junction memory including a first end and a second end;
- a first transistor including a control electrode, a first controlled electrode and a second controlled electrode;
- a second transistor including a control electrode, a first controlled electrode and a second controlled electrode;
- and
- a diode having a first end and a second end;
- wherein the second controlled electrode of the first transistor is coupled to the first end of the magnetic tunneling junction memory;
- wherein the second end of the magnetic tunneling junction memory is coupled to the first controlled electrode of the second transistor and the first end of the diode;
- wherein the control electrode of the first transistor is configured to be coupled to a word line;
- wherein the first controlled electrode of the first transistor is configured to be coupled to a bit line;
- wherein the control electrode of the second transistor is configured to be coupled to an input;
- wherein the second controlled electrode of the second transistor is configured to be coupled to a first source line;
- and
- wherein the second end of the diode is configured to be coupled to a second source line.
10 more elements
A method of forming a memory cell, the method comprising:
- providing a magnetic tunneling junction memory including a first end and a second end;
- providing a first transistor including a control electrode, a first controlled electrode and a second controlled electrode;
- providing a second transistor including a control electrode, a first controlled electrode and a second controlled electrode;
- providing a diode having a first end and a second end;
- coupling the second controlled electrode of the first transistor to the first end of the magnetic tunneling junction memory;
- coupling the second end of the magnetic tunneling junction memory to the first controlled electrode of the second transistor and the first end of the diode;
- coupling the control electrode of the first transistor to a word line;
- coupling the first controlled electrode of the first transistor to a bit line;
- coupling the control electrode of the second transistor to an input;
- coupling the second controlled electrode of the second transistor to a first source line;
- and
- coupling the second end of the diode to a second source line.
9 more elements
A method of operating a memory cell, the method comprising:
- providing said memory cell comprising:
- a magnetic tunneling junction memory including a first end and a second end;
- a first transistor including a control electrode, a first controlled electrode and a second controlled electrode;
- a second transistor including a control electrode, a first controlled electrode and a second controlled electrode;
- and
- a diode having a first end and a second end;
- wherein the second controlled electrode of the first transistor is coupled to the first end of the magnetic tunneling junction memory;
- wherein the second end of the magnetic tunneling junction memory is coupled to the first controlled electrode of the second transistor and the first end of the diode;
- wherein the control electrode of the first transistor is configured to be coupled to a word line;
- wherein the first controlled electrode of the first transistor is configured to be coupled to a bit line;
- wherein the control electrode of the second transistor is configured to be coupled to an input;
- wherein the second controlled electrode of the second transistor is configured to be coupled to a first source line;
- and
- wherein the second end of the diode is configured to be coupled to a second source line;
- and
- flowing a first write current through the magnetic tunneling junction in a first direction to write a first logic state in the magnetic junction memory;
- and
- flowing a second write current through the magnetic tunneling junction in a second direction opposite the first direction to write a second logic state in the magnetic junction memory.
15 more elements
Dependencies are inferred from the claim text.