Apparatuses and methods for reducing row address to column address delay

An apparatus including:

• a sense amplifier configured to, during a precharge phase and in response to an isolation signal, decouple a first gut node of the sense amplifier from a first digit line and decouple a second gut node of the sense amplifier from a second digit line after the first gut node and the second gut nodes have been precharged to a precharge voltage;
• and
• a decoder circuit configured to transition from an activation phase to the precharge phase in response to a precharge command, wherein during the precharge phase, the decoder circuit is configured to set the isolation signal to cause the sense amplifier to decouple the first gut node from the first digit line and decouple the second gut node from the second digit line after the first gut node and the second gut node are precharged to the precharge voltage, wherein the decoder circuit is further configured to transition from the precharge phase to a subsequent activation phase in response to receipt of an activate command, wherein, during the activation phase, the decoder circuit is further configured to cause the sense amplifier to perform a threshold voltage compensation operation to bias the first and second digit lines based on a threshold voltage difference between at least two circuit components of the sense amplifier and, after the threshold voltage compensation operation, to cause the sense amplifier to sense a data state of a memory cell coupled to one of the first or second digit lines.

A method, comprising:

• transitioning to a precharge phase in response to receipt of a precharge command at a memory;
• during the precharge phase:
• precharging first and second gut nodes of a sense amplifier of the memory to a precharge voltage starting at a first time;
• and
• decoupling the first gut node from a first digit line and decoupling the second gut node from a second digit line starting at a second time after the first time;
• transitioning from the precharge phase to an activation phase in response to receipt of an activate command after the second time;
• and
• during the activation phase:
• performing a threshold voltage compensation operation to bias the first and second digit lines based on a threshold voltage difference between at least two circuit components of the sense amplifier;
• and
• sensing a data state of a memory cell of the memory that is coupled to one of the first or second digit lines after performing the threshold voltage compensation operation.