Semiconductor memory device and operating method of semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsHun-Dae Choi, Hwapyong Kim
Life of this patent
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Abstract
Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.
Claims20
A semiconductor memory device, comprising:
- a memory cell array including memory cells;
- an address buffer configured to receive address information on the memory cells from an external device;
- a command buffer configured to receive a command for accessing the memory cells from the external device;
- a strobe buffer configured to receive a first signal and a second signal from the external device;
- and
- a data buffer configured to receive data from the external device, in synchronization with the first signal and the second signal,
- wherein the strobe buffer includes,
- a first buffer configured to receive the first signal,
- a second buffer configured to receive the second signal,
- a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and
- a corrector configured to be activated or inactivated in response to the detection signal and to correct the first signal received by the first buffer and the second signal received by the second buffer when activated in response to the detection signal.
A semiconductor memory device, comprising:
- a memory cell array including memory cells;
- an address buffer configured to receive address information on the memory cells from an external device;
- a command buffer configured to receive a command for accessing the memory cells from the external device;
- a control logic circuit configured to activate a first signal, in response to a write command for the memory cell array being received from the external device;
- a first strobe buffer configured to receive a first strobe signal and a second strobe signal from the external device, to compare a first phase of the first strobe signal with a second phase of the second strobe signal in response to the first signal being activated, to correct the first strobe signal and the second strobe signal in response to the first phase and the second phase being different from each other, and to output the corrected signals as a third strobe signal and a fourth strobe signal;
- a first data buffer configured to latch a data signal received from the external device in synchronization with the third strobe signal and the fourth strobe signal, in response to the first signal being activated;
- a second strobe buffer configured to output a third signal and a fourth signal to the external device, in response to a read command for the memory cell array being received from the external device;
- and
- a second data buffer configured to output second data to the external device in synchronization with the third signal and the fourth signal.
A method of operating a semiconductor memory device, comprising:
- receiving a write command at a command buffer of the semiconductor memory device;
- receiving address information associated with the write command at an address buffer of the semiconductor memory device;
- receiving a first strobe signal and a second strobe signal;
- after the receiving of the write command, correcting the first strobe signal and the second strobe signal, in response to a first phase of the first strobe signal being different from a second phase of the second strobe signal;
- receiving data at a data buffer of the semiconductor memory device, in synchronization with the first strobe signal and the second strobe signal;
- and
- writing the received data in memory cells of the semiconductor memory device corresponding to the address information.
Dependencies are inferred from the claim text.