Apparatuses and methods for performing logical operations using sensing circuitry
AssigneeMicron Technology, Inc.
InventorTroy A. Manning
Life of this patent
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Abstract
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.
Claims21
-20. (canceled)
A system, comprising:
- a host configured to generate instructions;
- and
- a memory device comprising an array of memory cells coupled to sensing circuitry comprising a first latch and a second latch, wherein the memory device is configured to:
- receive an instruction from the host;
- and
- execute the instruction to perform at least one of a NAND operation or an AND operation using data values stored in the array as inputs by controlling the sensing circuitry without transferring the data values externally from the memory device.
A method, comprising:
- providing an instruction to a memory device from a host, wherein the memory device comprises an array of memory cells coupled to sensing circuitry comprising a first latch and a second latch;
- and
- executing, on the memory device, the instruction to perform at least one of a NAND operation or an AND operation using data values stored in the array as inputs by controlling the first latch and the second latch without transferring the data values externally from the memory device.
An apparatus, comprising:
- a sense amplifier comprising a first latch coupled to a pair of complementary sense lines of an array of memory cells;
- a second latch configured to serve as an accumulator and coupled to the sense amplifier via a pair of pass transistors;
- and
- control circuitry configured to provide signals to the first latch and the second latch in association with performing at least one of a NAND operation or an AND operation using, as inputs, a first data value latched by the first latch at a first point in time and a second data value represented by a signal on at least one of the pair of complementary sense lines at a second point in time.
Dependencies are inferred from the claim text.