Semiconductor Device, and Display Device and Electronic Device Utilizing the Same

A semiconductor device comprising:

• a first transistor;
• a second transistor;
• a third transistor;
• a fourth transistor;
• and
• a fifth transistor,
• wherein:
• one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor;
• a gate of the first transistor is electrically connected to a first wiring;
• the one of the source and the drain of the first transistor is electrically connected to a gate of the third transistor;
• a gate of the first transistor is electrically connected to a second wiring;
• one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
• the other of the source and the drain of the third transistor is electrically connected to a third wiring;
• the other of the source and the drain of the fourth transistor is electrically connected to a fourth wiring;
• one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring;
• the other of the source and the drain of the fifth transistor is electrically connected to a fifth wiring;
• and
• a gate of the fifth transistor is electrically connected to a second wiring.

The display device comprising:

• a first transistor;
• a second transistor;
• a third transistor;
• a fourth transistor;
• and
• a fifth transistor,
• wherein:
• one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor;
• a gate of the first transistor is electrically connected to a first wiring;
• the one of the source and the drain of the first transistor is electrically connected to a gate of the third transistor;
• a gate of the first transistor is electrically connected to a second wiring;
• one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
• the other of the source and the drain of the third transistor is electrically connected to a third wiring;
• the other of the source and the drain of the fourth transistor is electrically connected to a fourth wiring;
• one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring;
• the other of the source and the drain of the fifth transistor is electrically connected to a fifth wiring;
• a gate of the fifth transistor is electrically connected to a second wiring;
• the first wiring is configured to be supplied with a first signal;
• the second wiring is configured to be supplied with a second signal;
• the third wiring is configured to be supplied with a third signal;
• and
• the fifth wiring is configured to be supplied with a first potential.